The present invention generally relates to a method for designing a layout of a semiconductor device. More particularly, the present invention relates to a method for designing a layout in such a manner as to make the layout of an interconnection structure easily changeable if the specifications of the device have been changed. The present invention also relates to a storage medium having stored thereon a program for executing such a layout designing method, and further relates to a semiconductor device with an easily modifiable interconnection structure.
As the functionality and performance of various microelectronic devices have been tremendously improved and as the size thereof has been drastically reduced over the past few years, the necessity of developing semiconductor devices for particular users (i.e., application specific integrated circuits (ASICs)) in a short time has been rapidly increasing. In order to further shorten the ASIC development time, IC""s with various types of arrangements, e.g., gate-array types and embedded-gate-array types, have been provided. An arrangement of the gate-array type is partially incorporated into an IC with the embedded-gate-array-type arrangement.
In an IC with the gate-array-type arrangement, a logic circuit is formed to satisfy the specifications designated by a particular user by interconnecting or routing a plurality of gates arranged in advance to form an array as a master slice. According to this designing method, the user""s designated specifications can be met only by designing the interconnection structure. Thus, it is possible to reduce the development cost and time.
In an IC with the embedded-gate-array-type arrangement, the gate-array-type arrangement is partially incorporated.
Depending on whether or not its specifications have been determined, functional circuits (also called simply xe2x80x9ccomponentsxe2x80x9d or xe2x80x9ccellsxe2x80x9d are classified into the two categories of: a fixed circuit section (including fixed components or cells); and a non-fixed circuit section (including non-fixed components or cells). A standard-cell-type arrangement is applied to the fixed circuit section, while the gate-array-type arrangement is applied to the non-fixed circuit section. After the specifications of the non-fixed circuit section have been determined, the gates, which have been formed like an array in the non-fixed circuit section, are routed as per the specifications determined. According to this designing method, fixed circuit sections, such as memory sections, can be fixed before the layout designing is started. Thus, to finish the overall circuit design, the designer has only to design the non-fixed circuit section, thus further shortening the development time. In addition, since the fixed circuit section may be implemented as an arrangement of standard cells, the number of components or cells that can be integrated per unit area increases compared to an IC with the gate-array-type arrangement. In other words, the area of a chip required for integrating the same number of components can be reduced. An LSI of the embedded-gate-array type is disclosed in U.S. Pat. No. 4,786,613, for example.
The meanings of basic terms as used in this specification will be defined with reference to FIG. 20. A xe2x80x9clayoutxe2x80x9d 900 defines a geometric or topographic arrangement for an LSI. The layout 900 for an LSI includes a component (or cell) layout 920 defining a functional circuit (or cell), and an interconnection layout 940 defining an xe2x80x9cinterconnectionxe2x80x9d. The component layout 920 includes a plurality of component planar layouts 922, 923, 924, 925 and 926, which define n-well, active region, polysilicon layer, p+-type doped region and n+-type doped region, respectively. The interconnection layout 940 also includes a plurality of interconnection planar layouts 942, 943, 944 and 945, which define contact holes, first set of interconnection lines, through holes and second set of interconnection lines, respectively. The xe2x80x9cinterconnectionxe2x80x9d includes not only interconnection lines within a plane, but also interlayer connections by way of through holes (or via holes). In fabricating a semiconductor device by ordinary photolithographic processes, a number of masks, corresponding to respective planar layouts, are produced.
However, no matter whether an IC is designed using the gate-array-type or embedded-gate-array-type arrangement, the time taken to define the layout design continues to increase with the increasing number of gates or interconnection layers provided. In addition, the cost and time taken to produce a mask is also increasing with such a complication of physical circuit design. A mask used to produce a fine-line pattern (e.g., with a design rule of 0.25 xcexcm or less), in particular, is much more expensive than a conventional mask (e.g., with a design rule of 0.35 xcexcm or more). Furthermore, along with an increase in number of layers in a multilevel interconnection structure, the number of masks required for fabricating a single semiconductor device is also considerably increasing (e.g., 6 or more masks are needed recently). Accordingly, such an increase in cost and time taken to produce the masks can now be regarded as a main factor increasing the cost and time taken to develop a semiconductor device.
Hereinafter, a conventional method for designing a layout for an LSI will be described with reference to FIG. 21.
FIG. 21 is a flowchart illustrating a conventional method for designing a modified layout for an LSI, which has been once designed, but should have the circuit design (interconnection structure) thereof partially changed after that.
First, in Step S1700, a layout for the LSI is designed based on a netlist N1 representing interconnection information according to initial specifications. At this point in time, an initial layout is produced according to the initial specifications. If the design need not be changed, then the initial layout is output and a mask (exactly, a set of masks) is produced based on the initial layout. The set of masks includes a plurality of masks associated with respective planar layouts included in the initial layout.
Next, in Step S1710, a netlist N2 representing modified interconnection information is made to reflect the change in circuit design.
Then, in Step S1720, a new layout is designed for the LSI based on the netlist N2, thereby producing a modified layout according to the changed specifications. The modified layout is produced totally independent of the initial layout. For example, in an LSI with the gate-array-type arrangement, all the interconnections are rerouted.
Subsequently, in Step S1730, the modified layout, corresponding to the netlist N2, is output. And based on the modified layout output, the masks are produced again.
The prior art layout designing method, however, has the following drawbacks. Hereinafter, it will be described specifically what problems are caused if the conventional layout designing method shown in FIG. 21 is applied to an LSI with the gate-array-type arrangement.
When the layout of the LSI with the gate-array-type arrangement is modified based on the netlist N2 reflecting the changed specifications, all the interconnections are rerouted. Accordingly, the number of process steps and the number of masks, which are required for re-designing the layout, cannot be reduced. In other words, the time and cost taken to modify the layout cannot be reduced. If several masks have already been produced based on the initial layout when it turns out that the layout should be modified, then all of those masks should be discarded and new masks should be produced over again. Furthermore, if a wafer (i.e., a master slice) has already been introduced into the LSI production line at that point in time, then all the half-finished products should be thrown away.
For example, even when some minor changes should be made in input/output signal transmission lines or pull-up components for a power supply, all the masks associated with respective interconnection layers should be produced once again according to the conventional layout designing method. In general, the larger the number of circuits integrated on a single chip, the more likely the specifications are changed. Under the circumstances such as these, even if the design of a circuit has been changed only slightly, the cost and time taken to produce masks tremendously increase, thus causing a serious problem.
An object of the present invention is providing a layout designing method enabling a designer to develop a semiconductor device in a shorter period of time.
Another object of the present invention is providing a storage medium having stored thereon a program for executing such a layout designing method.
Still another object of the present invention is providing a semiconductor device that can be designed in a shorter period of time.
A method for designing a layout of a semiconductor device according to the present invention includes the steps of: a) preparing a first layout corresponding to a first netlist and including a component layout and a number n of, or first to nth (where nxe2x89xa72), interconnection planar layouts to be sequentially stacked on the component layout; b) receiving a second netlist, which is different from the first netlist; c) selecting at least one of the interconnection planar layouts from the first layout, the number of the interconnection planar layouts selected being equal to or smaller than nxe2x88x921; and d) producing a second layout, corresponding to the second netlist, by changing the physical arrangement of the at least one interconnection planar layout selected. The second layout includes the component layout, the at least one interconnection planar layout with the changed arrangement, and the other interconnection planar layouts that have not been selected from the first layout.
In one embodiment of the present invention, the method may further include, prior to the step a), the steps of: receiving the first netlist; and producing the first layout based on the first netlist. Each of the number n of interconnection planar layouts included in the first layout may have a plurality of redundant interconnection patterns that are separated from each other and not included in a first interconnection structure defined by the first netlist. In the step d), the second layout may be produced such that at least one of the redundant interconnection patterns of the interconnection planar layout selected is included in a second interconnection structure defined by the second netlist.
In another embodiment of the present invention, the component layout may define at least one standard cell.
In still another embodiment, the component layout may define a plurality of macroblocks.
In still another embodiment, one of the number n of interconnection planar layouts may be selected from the first layout in the step c).
In still another embodiment, the interconnection planar layout selected may be the nth interconnection planar layout.
In still another embodiment, a kth (where 1xe2x89xa6kxe2x89xa7n) interconnection planar layout may be selected in the step c) from the number n of interconnection planar layouts belonging to the first layout. In the step d), if the second layout is produced with the kth interconnection planar layout changed, then information representing k and the second layout may be output. Alternatively, if the second layout is produced with the kth interconnection planar layout not changed, then the steps c) and d) may be repeatedly performed by substituting kxe2x88x921 for k until k becomes equal to one.
In still another embodiment, the method may further include the steps of: performing the step c) for all the possible combinations; performing the step d) for all the possible combinations obtained in the step c); and outputting a second layout set including information specifying the at least one interconnection planar layout selected and the second layout corresponding to the planar layout for each of the possible combinations.
A computer readable storage medium according to the present invention has stored thereon a program executable in a computer for performing the method for designing a layout of a semiconductor device according to the present invention.
A semiconductor device according to the present invention includes: a component layer, in which a plurality of components are formed; and a plurality of interconnection layers, which are stacked on the component layer and in which interconnection lines for electrically connecting the components to each other are formed. At least one of the interconnection layers includes a redundant interconnection line, which is formed in a region of the interconnection layer intersecting with an interconnection line formed in a layer overlying the interconnection layer, and which includes two conductor portions extending in such directions as intersecting with each other.
Another semiconductor device according to the present invention includes: a component layer, in which a plurality of components are formed; and a plurality of interconnection layers, which are stacked on the component layer and in which interconnection lines for electrically connecting the components to each other are formed. A plurality of redundant interconnection lines are arranged to form a regular pattern between interconnection lines formed in at least one of the interconnection layers.
According to the layout designing method of the present invention, when a circuit design should be modified to cope with a change in specifications, the layout of the circuit can be changed easily, thus shortening the time taken to develop a semiconductor device. For example, even when the circuit should be redesigned in accordance with a change in specifications after the layout has been once defined, a modified layout can be prepared quickly enough to cope with such a change. In addition, the layout can be modified in such a manner as to reflect the change in specifications only by changing a required minimum number of interconnection planar layouts. Accordingly, the time and cost to produce masks can be reduced. Furthermore, the interconnection planar layouts to be changed may be selected from only those located at highest possible levels, which correspond to masks used in later stages of a semiconductor device fabrication process. Thus, depending on how far the fabrication process has reached, half-finished products need not be thrown away and the time and cost required for the fabrication can be cut down.
A semiconductor device with redundant interconnection lines according to the present invention has such a structure as making the modification of layout easily implementable and optimizing the interconnection performance such as signal propagation delay.
The present invention provides (1) a layout designing method enabling a designer to develop a semiconductor device in a shorter time, (2) a storage medium having stored thereon a program for implementing the layout designing method, and (3) a semiconductor device that can be designed in a shorter time.